I was reviewing a Cypress data sheet for the CYW4390 and saw a line in the UART chapter saying that the total baud rate error budget for both ends had to be less than 2%. With a large dependence upon internal oscillators these days, it seemed a good time to discuss these error budgets. Is 2% reasonable or conservative?
First here is a quick back of the envelope calculation for link budget for UARTS. I will assume "perfect" rise & fall times, and 8, none, 1(8n1) framing.